| Building a memory board for the HP1000 A-Series Minicomputer
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This is a description of a memory board you can build yourself for your HP 1000 Minicomputer. The board has been built and tested on the A400 cpu, but should work on the A600 as well, but I have not tested that as I have no A600 CPU. It uses standard parts and one standard 5V or 3.3V, but 5V tolerant SIMM to provide 32Mb (16Mword) of memory.
It all started with an innocent question here and as my A400 only had 2Mb, I decided to see what I could do about it.
I decided to start with the schematic for the HP 12103D series board (1Mb) and take it from there.
Now, the documentation for the HP Boards is excellent, but I initially missed one crucial detail: Early vs late writes. The on-board memory on the A400 uses one, the array memory cards (HP12103A..K) another. This caused me a lot of grief and wasted months.
Started with a breadboard:
The original HP boards used 74S and some 74LS. Today we have a plethora of logic families, but I settled on 74ALS when available. The offer the same or better timings as 74S, but with out the fast edges of 74HCT or 74AHCT. Faster is not always better in case it causes crosstalk and ringing.
The 12103D boards had one "unobtainium" component. A Delay line. Fortunately is there a standard component available, the DS1100 delay line that comes in several varieties
This puppy almost works:
You can see how the test starts. Location 0 is read, then inverted, then written back, twice, then read. If this succeeds then there is a run of writing and reading a walking pattern.
GO+ 0ns RAS- 130ns ROWB+/COLB- 154ns LAT+ 178ns RAMW- 220ns GO- 228ns RAS+ 402ns RAMW+ 404ns GOLB+ 432ns LAT- 444ns CAS+ 468ns PAR- 504ns - Oh, had I only known...
I realised I needed to see more channels so I ended up with the KingstWiz LA 5032 analyser with almost enough channels and depth to capture almost the entire memory test. It also came with a nice SDK so I could write a parallel decoder for the HP1000 memory bus.
Board works, but not reliably. See below for reason. But enjoy the pretty picture first!
As I said earlier is there a crucial difference in how the A400 handles on-board and off-board RAM and yes, the trick where you make the on-board "transparent" disabled IS actually in the docs (A400 Memory control 4-3, bottom of page, 4-7 third paragraph). The difference is this: Pages 4-18, 4-19. The on-board RAM uses "Early write" where the DRAM outputs remain disabled during write. The Array cards use a "late write".Modern SIMMs do not support "late write"
All I needed was a slightly longer delay! New board now has two DS1100 100ns with jumper selects to pick a suitable timing.
The prototype board has an error! U4D should be an ALS08
Note that I have followed the descriptions in the HP docs, so RAS+ means that the signal is active high, whereas CAS- means active low.
The original 12103 boards has some fancy addressing which is not needed as one board fills up the entire 32Mb of an A400. The A400 on-board RAM is disabled by J2. Downside of a full 32Mb memory is that the RAM test takes up to a minute on an A400 so a provision exists to limit the RAM space to 8, 16 or 32Mb by JP1 and JP2. There is also JP3 in case you want to roll your own adressing. Also note J12 which normally should have jumpers in all 4 positions. As we have only one board, there is no need for the frontplane bus a flatcable connects the frontplane bus to the board.
All modern RAMs support CAS-before-RAS or CBR refresh. This is done by U9 and U12. They are triggered by the REF+ signal which creates a CBR sequence. The same REF+ lets U10 select that instead of the original RAS and CAS fed to the buffer U13
Signals from the frontplane bus are buffered by U3 and the GO signal is fed to the RAS flip-flop. The output is gated and fed to delay lines U11 and U15 to create CAS which is also gated by RAS in U2C to make sure they fall concurrently. A signal from TAP3 (3x20ns) is used to switch the ROW and COLUMN buffers by U4C and U14.
As addresses are clocked in RAS first and then CAS the timing of the ROW and COL buffers needs to be such that the ROW and COLUMN addresses are there and had time to stabilise. The top traces show the control signals for U20,21 and U22,23 respectively and the switch between ROW and COL is timed approximately halfway between RAS falling that clocks in the ROW address and CAS falling which clocks in the COLUMN. Looking at signals with the analogue channels is good as you will see overshoots and ringings that the digital channels might hide.
Data is read by the A400 on the falling edge of VALID
The SIMM is 32 bits, but only 17 are used for 16 data bits and parity. The rest of the data pins and connected to ground through 47k resistors to avoid floating pins. Address and RAS/CAS lines have series resistors to dampen ringing. Th current design supports single-sided SIMMs only as all RAS an CAS signals are driven in parallell by U13. Supporting dual-sided SIMMs is trivial and left as a exercise for the reader :)
The parity signal is buffered by U24 and controls the PCK- signal through an open-collector buffer U7. U5A is a flip-flop that is cleared by CRS-. Any parity error will clear the flip-flop and the led extinguishes.
It helps to bevel the edges of the "nose" of the edge contacts to 45 degrees to help it slide into the backplane contacts. Use a fine sandpaper and a block of wood when doing so and do not cut away more than necessary.
The board has tons of test points, ie J1, J5, J6 and they can be left unpopulated.
Note that U20, U21,U22, U23 are oriente the other way around. Sorry about that!
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There are tons of different SIMMs available from places like eBay and https://ram-co-shop.de. The one in the picture above is a 64Mb single-sided SIMM using KM44V16104BK-6 DRAMS. I have also tested SIMMs with GM71C17803Cj6, TMS417400ADJ, VG2617400Dj etc. All work and give varying amounts of memory. Ie the 64Mb SIMM mentioned above will give you 32Mb of memory. The board supports 5V or 3.3V SIMMS, but the DRAMS need to be 5V tolerant, but many older 3.3V DRAMS are. You just need to be careful and ask the seller what type of DRAMS the SIMM has. Regular SIMMs that work generally have 8 chips per side. If the SIMM you are looking at has 10 chips, then it is probably a parity SIMM which will not work.
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